FPGAs are used to implement large systems that include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, technology mapping, clustering, placement, and routing.
In the past, physical synthesis was optionally used to perform a series of circuit transformations to optimize the design of the system for one or more given goals. The goals may include optimizing a path to meet a specific user timing constraint, reducing area required to implement a circuit, reducing static or dynamic power consumption, increasing the routability of a design, or other goal. Unlike traditional synthesis, physical synthesis may take into account the technology and architecture of the target device and delays associated with signals on the target device while performing the circuit transformations to optimize the design of the system. Most of the delays in an FPGA circuit are due to the programmable routing network. These delays cannot be determined with great certainty until the routing step is completed. The traditional logic synthesis step of the FPGA CAD flow is responsible for creating a circuit implementation that will realize the functionality of a designer's hardware specification. At this early stage of the CAD flow, it is difficult to predict the delays of routed connections. Physical synthesis allows netlist transformations to be performed before and after clustering and placement. Physical synthesis's relatively late position in the CAD flow allows it to take advantage of more accurate estimates of the delays of routed connections available.